Tape automated bonding (TAB) has been used to electrically communicate with multi-terminal integrated circuit (IC) chips for many years. Examples of the use of such a technique may be reviewed by viewing references such as U.S. Pat. No. 4,209,355 covering the manufacture of bumped composite tape for automatic gang bonding of semiconductor devices which shows the use of an insulated strip on which a plurality of metal fingers are bonded, the fingers terminating in a configuration where each finger mates with an IC bonding pad.
A variety of lead configurations have been proposed for such TAB implementations. For example, in U.S. Pat. No. 4,390,598 there is shown a particular lead format for TAB formats in which individual leads have stretch loops to accommodate elongation of the loop as the lead is bonded to a substrate after inner lead bonds have been formed to an IC chip. Such a lead frame allows temporary connection and testing of the circuit prior to final lead formation and packaging.
An IC assembly which features TAB techniques and an etched double metal clad plastic carrier to allow the chip to be mounted directly to one side of a metallic base while a metallic lead frame is disposed on the opposite side may be seen in U.S. Pat. No. 4,459,607.
U.S. Pat. No. 4,564,582 shows a carrier tape used for automatically bonding IC devices on a substrate and having sets of finger leads and sprocket holes, the carrier tape being made from a metallic foil tape such as copper coated with a photo resist material which is exposed using a photo mask including patterns for sprocket holes and finger lead clusters.
Another example of the prior art is shown in U.S. Pat. No. 4,571,354 which discloses a method and apparatus for tape automated bonding of ICs wherein a support ring is formed in the feature window to provide a reinforcement for unsupported interconnection leads between the inner and outer lead bond sites.
A low cost process for bonding a plurality of integrated circuit die to a variety of die support frames using TAB process is described in U.S. Pat. No. 4,661,192, and a universal test circuit for integrated circuit packages that can be interconnected via both wire bonding and mass bonding and which functions as a test vehicle for TAB process may be seen in U.S. Pat. No. 4,684,884.
Still other examples of prior art designs in the subject area are U.S. Pat. Nos. 4,706,811 and 4,747,017 for their showing of surface mount packages formed by nesting an encapsulated TAB IC module in between two plastic rings snapped together.
All of these prior art references are concerned with unique problems dealing with high density IC packaging and testing. As the speed of electronic systems increases, so too does the need to minimize the chip-to-chip spacing. Multichip modules address this issue by packing many integrated circuits in a common package which allows them to be placed very closely together. While this approach enables a system to operate at very high frequencies, it also makes it more difficult to test the individual chips. This is a critical issue since as the number of chips per package increases, the yield of the multichip module becomes increasingly dependent upon the yield of the individual chips.
Tape automated bonding provides the best method of accommodating both of these requirements. TAB consists of a polyamide tape with a layer of copper bonded to one side. The copper is printed and etched to create a lead frame. The invention utilizes the technique of providing lead spacing around the inside of the frame that matches the pad pattern of the chip and the lead spacing around the outside of the frame is fanned out to facilitate testing. After testing, the chip and leads are cut out of the TAB tape and the chip is installed in the module. TAB enables chips to be packaged very closely together and also enables each chip to be fully tested "At Speed" prior to installation.
However, there are some drawbacks to implementing TAB interconnects. Separate dedicated TAB bonding equipment may be required since conventional wire bonders are often incompatible with the TAB process. The process also requires the pads on the chip to be "Bumped" (plated with approximately 5 mils of gold) in order to bond the tape to the chip, and each chip will require a separate TAB tape design since the TAB leads must be etched to match the chip pad pattern. The cost of purchasing TAB bonding equipment, developing TAB tape designs, and adding the additional process to bump chips prevents many manufacturers from implementing TAB.
It should be clear that a flexible chip interconnect, combining the benefits of both TAB and conventional wire bonding processes, would be a valuable advancement in the art. Like TAB, it would provide a means to fully test each chip prior to installation. However, it wouldn't require new equipment or the need to bump chips since it relies on conventional wire bonding techniques. This would allow manufacturers experienced in wire bonding to implement a fully testable interconnect system without expending large sums of money for new equipment. Another advantage is that it can provide a generic or non-custom interconnect for chips with a common die size, unlike TAB which must be etched to match the pad pattern of a specific chip. Thus, the system would allow several chips to use the same interconnect design.